With C30, in the compiler option, check "Enable large arrays".
With XC16, check "Allow arrays larger than 32K" in the Memory model.
Wednesday, April 26, 2017
Thursday, March 16, 2017
UART JTAG
XTAL = 20MHz
UART = 921,600
1. Setup UART
2. Test loopback
3. Test SPI
4. Test SPI loopback
=======
Program the Test Chip to Blink LED
Enter Enhanced ICSP
Exit ICSP
Send Instruction to IR, and Check IR Output
Read Device ID from DR
========
SET_ICSP_PINS arg[1] = pin states
<7 – 4> unused
<3> PGD logic level
<2> PGC logic level
<1> 1= PGD input, 0= output
<0> 1= PGC input, 0= output
========
FASTDATA 0xF..FF20.0000 to 0xF..FF20.000F
========
Ref Clk: 921,600: 1-182, 2-364
PLLMULT: Ref:20MHz(Sys)=>1Hz
1=>3Hz, 0=>19Hz, 2=>20Hz, 3=>6Hz, 4=>8Hz, 5=>12Hz, 6=>19Hz
1=>3Hz, 0=>19.38Hz, 2=>20Hz, 3=>4.42Hz, 4=>5.89Hz, 5=>12Hz, 6=>17.7Hz
========
ICSP speed: 10MHz (P1,TPGC)
MTAP speed: 12MHz
ETAP speed: 10MHz
========
JTAGEN bit: http://www.microchip.com/forums/m947541.aspx
Debug Vector
UART = 921,600
1. Setup UART
2. Test loopback
3. Test SPI
4. Test SPI loopback
=======
Program the Test Chip to Blink LED
Enter Enhanced ICSP
Exit ICSP
Send Instruction to IR, and Check IR Output
Read Device ID from DR
========
SET_ICSP_PINS arg[1] = pin states
<7 – 4> unused
<3> PGD logic level
<2> PGC logic level
<1> 1= PGD input, 0= output
<0> 1= PGC input, 0= output
========
FASTDATA 0xF..FF20.0000 to 0xF..FF20.000F
========
Ref Clk: 921,600: 1-182, 2-364
PLLMULT: Ref:20MHz(Sys)=>1Hz
1=>3Hz, 0=>19Hz, 2=>20Hz, 3=>6Hz, 4=>8Hz, 5=>12Hz, 6=>19Hz
1=>3Hz, 0=>19.38Hz, 2=>20Hz, 3=>4.42Hz, 4=>5.89Hz, 5=>12Hz, 6=>17.7Hz
========
ICSP speed: 10MHz (P1,TPGC)
MTAP speed: 12MHz
ETAP speed: 10MHz
========
JTAGEN bit: http://www.microchip.com/forums/m947541.aspx
Debug Vector
Thursday, February 9, 2017
PIC32MM support - PICkit 2
Code Memory Size
Device
|
Row Size
(Words)
|
Page Size
(Words)
|
Boot Flash Size
|
PIC32MM
|
64
|
512
|
0x1FC00000-0x1FC016FF (5.75KB)
|
PIC32MX1/2
|
32
|
256
|
0x1FC00000-0x1FC00BFF (3KB)
|
PIC32MX3/4/6/7
|
128
|
1024
|
0x1FC00000-0x1FC02FFF (12KB)
|
int progMemP32 = (int)Pk2.DevFile.PartsList[Pk2.ActivePart].ProgramMem;
int bootMemP32 = (int)Pk2.DevFile.PartsList[Pk2.ActivePart].BootFlash;
ProgramMem = (0x10000+0x1700)/4 = 17856 (including boot flash)
BootFlash = 0x1700/4= 1472
BootFlash = 0x1700/4= 1472
PE Command
remove 0x03: WORD_PROGRAM
add 0x0E: DOUBLE_WORD_PGRM
Configuration Bits: Double Word
FSIGN (0x1FC0.17E0) 0x7FFF (must)
Code Execution from RAM: A000:0800 == not required ==
Set CFGCON.EXECADDR<7:0> to 0x02
CFGCON at 0xBF80.3B00
PICkitFunctions.searchDevice
=========================
Move PE Loader to 0xA000.0200, PE to 0xA000.0300
ImportHex - 90%, UserID (WIP)
ExportHex
Configuration Bits - DialogConfigEdit - OK(display)
=============================
PE Loader: (swap HI/LO word, 41A3, FF20, 41A5, DEAD, 6A30, 6930...)
ChipEraseScript:
Code Execution from RAM: A000:0800 == not required ==
Set CFGCON.EXECADDR<7:0> to 0x02
CFGCON at 0xBF80.3B00
PICkitFunctions.searchDevice
=========================
Move PE Loader to 0xA000.0200, PE to 0xA000.0300
v
|
PIC32BlankCheck
| |
v
| PIC32Read | |
v
| PIC32CRC | |
v
| PIC32Verify | |
v
| PIC32Erase | |
| Change the ChipEraseScript | ||
v
| PIC32Write | |
| if the JTAGEN is programmed, the MCHP TAP controller must be selected immediately after any PROGRAM command. This can be done by using a SendCommand(MTAP_SW_MTAP) pseudo operation. After 400 us, the EJTAG TAP controller can be selected again by calling the SendCommand(MTAP_SW_ETAP) pseudo operation. -- ch 16.3 | ||
ImportHex - 90%, UserID (WIP)
ExportHex
Configuration Bits - DialogConfigEdit - OK(display)
=============================
PE Loader: (swap HI/LO word, 41A3, FF20, 41A5, DEAD, 6A30, 6930...)
ChipEraseScript:
$JT2_SENDCMD 07 //<--- SendCMD(MTAP_CMD) $JT2_XFERDATA8_LIT FC //<--- Xferdata(MCHP_ERASE) $JT2_XFERDATA8_LIT D0 //<--- Xferdata(MCHP_DE_ASSERT_RST) $DELAY_LONG 4A
===== Notes: JTAG =====
MTAP
- MTAP_SW_MTAP[5h0x04]
- MTAP_SW_ETAP[5h0x05]
- MTAP_IDCODE[5h0x01]
- MTAP_COMMAND[5h0x07]
- MCHP_STATUS
- MCHP_ASSERT_RST
- MCHP_DE_ASSERT_RST
- MCHP_ERASE
EJTAG
- ETAP_ADDRESS[5h0x08]
- ETAP_DATA[5h0x09]
- ETAP_CONTROL[5h0x0A]
- ETAP_EJTAGBOOT[5h0x0C]*
- ETAP_FASTDATA[5h0x0E]*
# XferFastData
ETAP_FASTDATA
# XferInstruction
ETAP_CONTROL
ETAP_DATA
ETAP_CONTROL
Thursday, January 26, 2017
Monday, January 16, 2017
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